The present invention generally relates to the design of field effect transistors (FETS) and, more particularly, to a method of mitigating charge on the surface of Silicon-on-Insulator (SOI) products.
As is known in the art, transistors such as metal oxide silicon (MOS) transistors, have been formed in isolated regions of a semiconductor body such as an epitaxial layer which was itself formed on a semiconductor, typically bulk silicon, substrate. With an n-channel MOS field effect transistor (FET), the body is of p-type conductivity and the source and drain regions are formed in the p-type conductivity body as N+ type conductivity regions. With a p-channel MOSFET, the body, or epitaxial layer, is of n-type conductivity and the source and drain regions are formed in the n-type conductivity body as P+ type conductivity regions. It has been suggested that the semiconductor body, or layer, be formed on an insulating substrate, or over an insulation layer formed in a semiconductor substrate. Such technology sometimes is referred to as Silicon-on-Insulator (SOI) technology. Silicon-on-Insulator MOS technologies have a number of advantages over bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N+ to P+ spacing and hence higher packing density due to ease of isolation; and higher xe2x80x9csoft errorxe2x80x9d upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Silicon-on-Insulator technology is characterized by the formation of a thin silicon layer for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources in drains are formed by, for example, implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor (e.g. metal) layer structure. Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). However, the floating body can introduce dynamic instabilities in the operation of such a transistor.
An SOI field effect transistor combines two separated immunity groups, generally formed by implantation, constituting the source and drain of the transistor with the general region (device body) between them covered by a thin gate insulator and a conductive gate. Typically no electrical connection is made to the channel region and therefore the body is electrically floating. Because the source and drain regions normally extend entirely through the thin silicon layer, the electrical potential of the body is governed by Kirchoff""s current law, wherein the sum of the currents flowing into the body equals the sum of the currents flowing out of the body. Because the channel potential is dependent on the body voltage, the device threshold voltage varies as a function of the body voltage.
In SOI transistors there is a lack of a bulk silicon or body contact to the MOS transistor. In some devices, it is desirable to connect the p-type conductivity body in the case of an n-channel MOSFET, or the n-type conductivity body in the case of a p-channel MOSFET, to a fixed potential. This prevents various hysteresis effects associated with having the body potential xe2x80x9cfloatxe2x80x9d relative to ground. Additionally, this mitigates a build up of charge on the active silicon layer that can occur during fabrication and operation of the SOI transistors. Therefore, improvements for mitigating the aforementioned problems with SOI devices is desirable.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to formation of a ground contact on an SOI product to mitigate charge buildup on the surface of the SOI device. A ground contact is formed from a top insulating layer to a bottom silicon layer to dissipate charge buildup. The ground contact extends through the insulating layer, a stop layer, a trench isolation region and an oxide layer to the bottom silicon layer. The ground contact is fabricated along with the formation of local interconnects. The ground opening is formed prior to the vias and trenches for forming contact patterns. Although, the resist will flow into the ground opening during the standard contact mask, the large size of the ground contact will help in the resist being removed easily. Additionally, since the number of ground contacts is significantly smaller than the actual contacts difficulty in removing the resist is mitigated.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative examples of the invention. These examples are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.